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HT95C200/20P/300/30P
Preliminary
Features
* Provide MASK type and OTP type version * Operating voltage range: - FSK: 3.0V~5.5V - Others: 2.4V~5.5V * Program ROM: 8K16 bits * Data RAM: - HT95C300/30P: 21128 bits - HT95C200/20P: 11528 bits * Up to 28 bidirectional I/O lines * 16-bit table read instructions * Eight-level subroutine nesting * Timer: - Two 16-bit programmable Timer/Event Counter - Real time clock (RTC) - Watchdog Timer (WDT) * Programmable frequency divider (PFD) * Dual system clock: 32768Hz, 3.58MHz * Four operating modes: Idle mode, Sleep mode, * Built-in 3.58MHz DTMF Generator * Built-in FSK decoder: - Supports Bell 202 and V.23 - Supports ring and line reversal detection * LCD driver: - HT95C300/30P: 48 seg.16 com. - HT95C200/20P: 24 seg.16 com. - Support 16 or 8 common driver pins - HT95C300/30P: 12 segments can per nibble op-
8-Bit CID Type Phone Controller MCU
tion to bidirectional I/O lines
- HT95C200/20P: 8 commons can per byte option to
bidirectional I/O lines
- LCD contrast can be adjusted by software or exter-
nal resistor
- Support two LCD frame frequency 64Hz, 128Hz * Built-in Low Battery detector * All instructions in one or two machine cycles * Built-in dialer I/O * 128-pin QFP package
Green mode and Normal mode
* Up to 1.117ms instruction cycle with 3.58MHz system
clock
Applications
* Deluxe Feature Phone * Caller ID Phone * Cordless Phone * Fax and answering machines * Other communication system
General Description
The HT95C200/20P/300/30P are 8-bit high performance RISC-like microcontrollers with built-in DTMF generator, FSK decoder and dialer I/O which provide MCU dialer implementation or system control features for telecom product application. The phone controller has a built-in program ROM, data RAM, LCD driver and a maximum of 28 I/O lines for high end products design. In addition, for power management purpose, it has a built-in frequency up conversion circuit (32768Hz to 3.58MHz) which provides dual system clock and four types of operation modes. For example it can operate with low speed system clock rate of 32768Hz in green mode with little power consumption. It can also operate with high speed system clock rate of 3.58MHz in normal mode for high performance operation. To ensure smooth dialer function and to avoid MCU shut-down in extreme low voltage situation, the dialer I/O circuit is built-in to generate hardware dialer signals such as on-hook, hold-line and hand-free. Built-in real time clock and programmable frequency divider are provided for additional fancy features in product developments. The device is best suitable for feature phone products that comply with versatile dialer specification requirements of different areas or countries.
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Preliminary
Selection Table
Part No. HT95A200 HT95A20P HT95A300 HT95A30P HT95L100 HT95L10P HT95L200 HT95L20P HT95L300 HT95L30P HT95C200 HT95C20P HT95C300 HT95C30P Operating Program Data Normal Dialer Voltage Memory Memory I/O I/O 2.4V~5.5V 2.4V~5.5V 2.4V~5.5V 2.4V~5.5V 2.4V~5.5V 2.4V~5.5V 2.4V~5.5V 4K16 8K16 4K16 8K16 8K16 8K16 8K16 11528 21128 11528 11528 21128 11528 21128 28 28 16~20 20~28 16~28 20~28 16~28 8 8 8 8 8 8 8 LCD 3/4 3/4 168~208 248~2416 3616~4816 248~2416 3616~4816 Timer 16-bit2 16-bit2 16-bit2 16-bit2 16-bit2 16-bit2 16-bit2 Stack 8 8 8 8 8 8 8
HT95C200/20P/300/30P
External Interrupt 4 4 4 4 4 4 4
DTMF Generator O O O O O O O
FSK Receiver 3/4 3/4 3/4 3/4 3/4 O O
Package 48SSOP 48SSOP 64QFP 100QFP 100QFP 128QFP 128QFP
Note: Part numbers suffixed with P are OTP devices, all others are mask version devices.
Block Diagram
PowerDown D e te c to r & R e s e t C ir c u it P ro g ra m C o u n te r P ro g ra m ROM ST ST ST ST ST ST ST ST AC AC AC AC AC AC AC AC K0 K1 K2 K3 K4 K5 K6 K7
RES
32768H z
In te rru p t C ir c u it IN T C 0 IN T C 1
TM R1 TM R1C
M U
IN T /T M R 1 X 32768H z M U X c lo c k /4 PA0~PA7 TM R0
RTC
In s tr u c tio n R e g is te r
TM R0 TM R0C MP0 MP1 M U X DATA M e m o ry PA PAC PB PBC PD PDC PE PEC 32768H z W DT OSC S y s te m C lo c k /4 M U X W DTS W D T P r e s c a le r DTM . G e n e ra to r
S y s te m
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r ACC
MUX
PB0~PB7
STATUS
PD 0~PD 7
S h ifte r PE0~PE3
X1 X2 XC H.I H.O HDI HDO HKS PO DNPO XM UTE VDD2 VSS2 VDD VSS
O S C C ir c u it
DTM .
3 .5 8 M H z .SK D ecoder 32768H z o r 3 .5 8 M H z /4 T IP R IN G RDETI R T IM E
D ia le r I/O
Power S u p p ly
Low B a tte ry D e te c to r
L C D D r iv e r 9 5 C 3 0 0 /3 0 P : 4 8 (4 4 ,4 0 ,3 6 ) 1 6 (8 ) 9 5 C 2 0 0 /2 0 P : 2 4 1 6 (8 )
P.D
M U S IC
L B IN
C O M 0~C O M 15 SEG 0~SEG 47 VLC D
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Preliminary
Pin Assignment
C C C C
HT95C200/20P/300/30P
NC
1 2 3 4 5 6 7 8 9
128 127126 125124 123122121120119118117 116115114113112111110109108107106105104 103 102 101 100 99 98 97 96 95 94 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 93 92 91 90 89 88 87 86
C SEG2 SEG1 SEG0 O M 15 O M 14 O M 13 O M 12 O M 11 O M 10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 NC VDD2 R T IM E RDETI R IN G T IP VSS2 NC NC NC NC SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE NC NC NC NC G3 G4 G5 G6 G7 G8 G9 G1 G1 G1 G1 G1 G1 G1 G1 G1 G1 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 G3 G3 G3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2
C
NC NC NC NC NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 XM UTE DNPO PO HKS HDO HDI H.O H.I VSS VDD IN T /T M R 1 NC NC NC NC NC
H T 9 5 C 3 0 0 /3 0 P 1 2 8 Q . P -A
85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
NC SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG VLC MUS RES TM R DTM L B IN XC X1 X2 NC D 33 34 35 3 6 /P 3 7 /P 3 8 /P 3 9 /P 4 0 /P 4 1 /P 4 2 /P 4 3 /P 4 4 /P 4 5 /P 4 6 /P 4 7 /P . IC 0 D0 D1 D2 D3 D4 D5 D6 D7 E0 E1 E2 E3
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Preliminary
CO CO CO CO CO CO CO CO M M M M M M M M
HT95C200/20P/300/30P
NC
1 2 3 4 5 6 7 8 9
128 127126 125124 123122121120119118117 116115114113112111110109108107106105104 103 102 101 100 99 98 97 96 95 94 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 93 92 91 90 89 88 87 86
NC NC COM9 COM8 7 /P D 7 6 /P D 6 5 /P D 5 4 /P D 4 3 /P D 3 2 /P D 2 1 /P D 1 0 /P D 0 NC NC NC NC NC NC NC NC VDD2 R T IM E RDETI R IN G T IP VSS2 NC NC NC NC NC NC NC NC NC NC NC NC COM COM COM COM COM COM SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG NC NC NC NC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 10 11 12 13 14 15
NC NC NC NC NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 XM UTE DNPO PO HKS HDO HDI H.O H.I VSS VDD IN T /T M R 1 NC NC NC NC NC
H T 9 5 C 2 0 0 /2 0 P 1 2 8 Q . P -A
85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
NC NC NC NC SEG SEG SEG SEG SEG SEG SEG SEG PE0 PE1 PE2 PE3 VLC MUS RES TM R DTM L B IN XC X1 X2 NC D 16 17 18 19 20 21 22 23 . IC 0
Pin Description
Pin Name CPU VDD VDD2 VSS VSS2 X1 X2 XC RES I O I I 3/4 3/4 Positive power supply Positive power supply for FSK decoder Negative power supply, ground Negative power supply for FSK decoder, ground A 32768Hz crystal (or resonator) should be connected to this pin and X2. A 32768Hz crystal (or resonator) should be connected to this pin and X1. External low pass filter used for frequency up conversion circuit. Schmitt trigger reset input, active low. Schmitt trigger input for external interrupt or Timer/Event Counter 1. No internal pull-high resistor. For INT: Edge trigger activated on a falling edge. For TMR1: Activated on falling or rising transition edge, selected by software. Schmitt trigger input for Timer/Event Counter 0. No internal pull-high resistor. Activated on falling or rising transition edge, selected by software. I/O Description
INT/TMR1
I
TMR0
I
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Preliminary
Pin Name LCD Driver SEG0~SEG23 SEG24~SEG35 SEG36~SEG47 (PD0~PD7, PE0~PE3) COM0~COM7 (PD0~PD7) COM8~COM15 VLCD Normal I/O PA0~PA7 I/O O O O or I/O O or I/O O I LCD panel segment outputs. I/O Description
HT95C200/20P/300/30P
LCD panel segment outputs. (HT95C300/30P only) LCD panel segment outputs. (HT95C300/30P only) SEG36~SEG39, SEG40~SEG43 and SEG44~SEG47 can be nibble optioned to PD0~PD3, PD4~PD7 and PE0~PE3 by software. LCD panel common outputs. HT95C300/30P: Can be optioned to COM0~COM7 or unused. HT95C200/20P: Can be optioned to COM0~COM7 or PD0~PD7. All these are optioned by software. LCD panel common outputs. LCD driver power source. Bidirectional 8-bit input/output ports. Schmitt trigger input or CMOS output. See mask option table for pull-high and wake-up function Bidirectional 8-bit input/output ports. Schmitt trigger input or CMOS output. See mask option table for pull-high function Bidirectional 8-bit input/output ports. Schmitt trigger input and CMOS output. HT95C300/30P: PD0~PD3 and PD4~PD7 can be per nibble optioned to SEG36~SEG39 and SEG40~SEG43 by software. HT95C200/20P: PD0~PD7 can be optioned to COM0~COM7 by software. See mask option table for pull-high function Bidirectional 4-bit input/output ports. Schmitt trigger input and CMOS output. HT95C300/30P: PE0~PE3 can be per nibble optioned to SEG44~SEG47 by software. HT95C200/20P: Fixed for PE0~PE3. See mask option table for pull-high function Schmitt trigger input structure. An external RC network is recommended for input debouncing. This pin is pulled low with internal resistance of 200kW typ. CMOS output structure. Schmitt trigger input structure. An external RC network is recommended for input debouncing. This pin is pulled high with internal resistance of 200kW typ. CMOS output structure. This pin detects the status of the hook-switch and its combination with HFI/HDI can control the PO pin output to make or break the line. CMOS output structure controlled by HKS and HFI/HDI pins and which determines whether the dialer connects or disconnects the telephone line. NMOS output structure. NMOS output structure. Usually, XMUTE is used to mute the speech circuit when transmitting the dialer signal.
PB0~PB7
I/O
PD0~PD7
O or I/O
PE0~PE3
O or I/O
Dialer I/O (See the Dialer I/O function) HFI HFO HDI HDO HKS PO DNPO XMUTE I O I O I O O O
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Preliminary
Pin Name Peripherals DTMF MUSIC TIP RING RDETI RTIME LBIN O O I I I I/O I I/O Description
HT95C200/20P/300/30P
This pin outputs dual tone signals to dial out the phone number. The load resistor should not be less than 5kW. This pin outputs the single tone that generated by the PFD generator. Input pin connected to the tip side of the twisted pair wires. It is internally biased to 1/2 VDD when the device is in power-up mode. This pin must be DC isolated from the line. Input pin connected to the ring side of the twisted pair wires. It is internally biased to 1/2 VDD when the device is in power-up mode. This pin must be DC isolated from the line. This pin detects ring energy on the line through an attenuating network. Schmitt trigger input and NMOS output pin which functions with RDETI pin to make an RC network that performs ring detection function. This pin detects battery low through external R1/R2 to determine threshold voltage.
Absolute Maximum Ratings
Supply Voltage ........................................-0.3V to 5.5V Input Voltage .............................. VSS-0.3 to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-25C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Electrical Characteristics
Symbol CPU IIDL Idle Mode Current 5V 32768Hz off, 3.58MHz off, CPU off, LCD off, WDT off, no load 32768Hz on, 3.58MHz off, CPU off, LCD off, WDT off, no load 32768Hz on, 3.58MHz off, CPU on, LCD off, WDT off, no load 32768Hz on, 3.58MHz on, CPU on, LCD on, WDT on, DTMF generator off, FSK decoder off, no load 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2 Parameter Test Conditions VDD Conditions Min. Typ. Max.
Ta=25C Unit
mA
ISLP
Sleep Mode Current
5V
3/4
3/4
30
mA
IGRN
Green Mode Current
5V
3/4
3/4
50
mA
INOR
Normal Mode Current
5V
3/4
3/4 3/4 3/4 6 -3 30 1.15
3
mA
VIL VIH IOL IOH RPH VLBIN
I/O Port Input Low Voltage I/O Port Input High Voltage I/O Port Sink Current I/O Port Source Current Pull-high Resistor Low Battery Detection Reference Voltage
5V 5V 5V 5V 5V 5V
0 4 4 -2 10 1.10
1 5 3/4 3/4 3/4 1.20
V V mA mA kW V
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Preliminary
Symbol LCD Driver VLCD ILCD Dialer I/O IXMO IOLXM IHKS RHFI RHDI IOH2 IOL2 IOH3 IOL3 IOH4 IOL4 IOL5 XMUTE Leakage Current XMUTE Sink Current HKS Input Current HFI Pull-low Resistance HDI Pull-high Resistance HFO Source Current HFO Sink Current HDO Source Current HDO Sink Current PO Source Current PO Sink Current DNPO Sink Current 2.5V XMUTE pin=2.5V 2.5V XMUTE pin=0.5V 2.5V HKS pin=2.5V 2.5V VHFI=2.5V 2.5V VHDI=0V 2.5V VOH=2V 2.5V VOL=0.5V 2.5V VOH=2V 2.5V VOL=0.5V 2.5V VOH=2V 2.5V VOL=0.5V 2.5V VOL=0.5V 3/4 3/4 3/4 3/4 3/4 3/4 3/4 5V 3/4 VDTMF=0.5V Row group, RL=5kW THD-23dB Row group=0dB RL=5kW 3/4 3/4 3/4 3/4 LCD Panel Power Supply LCD Operation Current 3/4 3/4 3/4 VLCD=5V, 32768Hz, no load Parameter Test Conditions VDD Conditions
HT95C200/20P/300/30P
Min. Typ. Max. Unit
3/4 3/4 3/4 1 3/4 3/4 3/4 -1 1 -1 1 -1 1 1
3 3/4 3/4 3/4 3/4 200 200 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 155 3/4 2 -30 -45 1200 20
5 100
V mA mA mA mA kW kW mA mA mA mA mA mA mA
1 3/4 0.1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0.7VDD 3/4 180 3/4 3 -23 3/4 1212 3/4
DTMF Generator VTDC VTOL VTAC RL ACR THD DTMF Output DC Level DTMF Sink Current DTMF Output AC Level DTMF Output Load Column Pre-emphasis Tone Signal Distortion 0.45VDD 0.1 120 5 1 3/4 -40 1188 3/4 V mA mVrms kW dB dB
FSK Decoder Input Sensitivity: TIP, RING Transmission Rate S/N Signal to Noise Ratio Band-pass Filter Frequency Response Relative to 1700Hz @ 0dBm 60Hz 550Hz 2700Hz 3300Hz Carrier Detect Sensitivity tSUPD Power Up to FSK Signal Set Up Time dBm baud dB
3/4
3/4
3/4 3/4 3/4 3/4 3/4 15
-64 -4 -3 -34 -48 3/4
3/4 3/4 3/4 3/4 3/4 3/4
dB
3/4 3/4
3/4 3/4
dBm ms
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Preliminary
Functional Description
Execution flow The system clock for the telephone controller is derived from a 32768Hz crystal oscillator. A built-in frequency up conversion circuit provides dual system clock, namely; 32768Hz and 3.58MHz. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme causes each instruction to be effectively executed in a instruction cycle. If an instruction changes the program counter, two instruction cycles are required to complete the instruction. Program counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of pro-
HT95C200/20P/300/30P
gram memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by 1. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the program counter manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed to the next instruction. The program counter lower order byte register (PCL:06H) is a readable and write-able register. Moving data into the PCL performs a short jump. The destinaT2 T3 T4 T1 T2 T3 T4
S y s te m
C lo c k
T1
T2
T3
T4
T1
PC
PC
PC+1
PC+2
. e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
. e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
. e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution flow
Mode Initial reset External interrupt Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Peripheral interrupt RTC interrupt Dialer I/O interrupt Skip Loading PCL Jump, call branch Return from subroutine
Program Counter *12 0 0 0 0 0 0 0 *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Program Counter+2 *12 #12 S12 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Note: *12~*0: Program counter bits #12~#0: Instruction code bits
S12~S0: Stack register bits @7~@0: PCL bits
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Preliminary
tion will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 819216 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 0000H
HT95C200/20P/300/30P
from a Timer/Event Counter 0 overflow, the Timer/Event Counter 0 interrupt is enabled and the stack is not full, the program begins execution at location 0008H.
* Location 000CH
This location is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, the Timer/Event Counter 1 interrupt is enabled and the stack is not full, the program begins execution at location 000CH.
* Location 0010H
This area is reserved for the initialization program. After chip power-on reset or external reset or WDT time-out reset, the program always begins execution at location 0000H.
* Location 0004H
This area is reserved for the external interrupt service program. If the INT/TMR1 input pin is activated, the external interrupt is enabled and the stack is not full, the program begins execution at location 0004H.
* Location 0008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results
000H 004H 008H 00C H 010H 014H 018H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e P e r ip h e r a l in te r r u p t s u b r o u tin e R T C in te r r u p t s u b r o u tin e D ia le r I/O in te r r u p t s u b r o u tin e P ro g ra m ROM
This location is reserved for the peripherals interrupt service program. The peripherals include a DTMF generator and FSK decoder. When the DTMF generator is operated in burst mode, it will generate an interrupt after 1 burst cycle is finished. When the FSK decoder detects a ringer or line reversal or FSK carrier signal or FSK packet data, the FSK interrupt is also generated. If these interrupts occurred, the peripheral interrupt is enabled and the stack is not full, the program begins execution at location 0010H. The programmer could distinguish from these interrupts from the DTMFC and FSKS register.
* Location 0014H
This location is reserved for real time clock (RTC) interrupt service program. When RTC generator is enabled and time-out occurs, the RTC interrupt is enabled and the stack is not full, the program begins execution at location 0014H.
* Location 0018H
This location is reserved for the HKS pin edge transition or HDI pin falling edge transition or HFI pin rising edge transition. If this condition occurs, the dialer I/O interrupt is enabled and the stack is not full, the program begins execution at location 18H. Table location Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, and the higher-order byte of the table word is transferred to TBLH. The table Table Location
n00H n..H
L o o k - u p ta b le ( 2 5 6 w o r d s )
1...H
L o o k - u p ta b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to 1 E H
Program memory
Instruction(s) TABRDC [m] TABRDL [m]
*12 P12 1
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Note: *12~*0: Table location bits @7~@0: Table pointer bits
P12~P8: Current program counter bits
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pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors will then occur. Hence, simultaneously using the table read instruction in the main routine and the ISR should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed-up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements. Stack register This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor write-able. The activated level is indexed by the stack pointer (SP) and is neither readable nor write-able. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and an interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited even if this interrupt is enabled. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature pre-
HT95C200/20P/300/30P
vents stack overflow allowing the programmer to use the structure more easily. If the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return addresses are stored). Data memory The data memory is divided into four functional groups: special function registers, embedded control register, LCD display memory and general purpose memory. Most are read/write, but some are read only. The special function registers is located from 00H to 1FH. The embedded control register are located in the memory areas from 20H to 3FH. The remaining space which are not specified on the following table before the 40H are reserved for future expanded usage and reading these locations will get 00H. The general purpose data memory is divided into 11 banks (HT95C300/30P) or 6 banks (HT95C200/20P). The banks in the RAM are all addressed from 40H to 0FFH and they are selected by setting the value of the bank pointer (BP). All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0 or MP1). The bank1~bank10 are only indirectly accessible through memory pointer 1 register (MP1). The LCD display memory is located at bank 1BH. They can be read and written to by the indirect addressing mode using memory pointer 1 (MP1). To turn the display On or Off, a 1 or 0 is written to the corresponding bit of the memory area.
Special register, embedded control register, LCD display memory and general purpose RAM BP Address Function Description
Special function register 00 00 00 00 00 00 00 00 00 00 00 00 00 01 02 03 04 05 06 07 08 09 0A 0B IAR0 MP0 IAR1 MP1 BP ACC PCL TBLP TBLH WDTS STATUS INTC0 Indirect addressing register 0 Memory pointer register 0 Indirect addressing register 1 Memory pointer register 1 Bank pointer register Accumulator Program counter lower-order byte register Table pointer Table higher-order byte register Watchdog Timer option setting register Status register Interrupt control register 0
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BP 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Address 0C 0D 0E 0F 10 11 12 13 14 15 16 18 19 1A 1B 1E Function TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC DIALERIO PD PDC PE PEC INTC1
HT95C200/20P/300/30P
Description Timer/Event Counter 0 high-order byte register Timer/Event Counter 0 low-order byte register Timer/Event Counter 0 control register Timer/Event Counter 1 high-order byte register Timer/Event Counter 1 low-order byte register Timer/Event Counter 1 control register Port A data register Port A control register Port B data register Port B control register Dialer I/O register Port D data register Port D control register Port E data register (bit3~bit0) Port E control register (bit3~bit0) Interrupt control register 1
Embedded control register 00 00 00 00 00 00 00 00 00 00 00 00 20 21 22 24 26 28 29 2A 2B 2D 2E 2F DTMFC DTMFD LINE RTCC MODE LCDIO FSKC FSKS FSKD LCDC PFDC PFDD DTMF generator control register DTMF generator data register Line control register Real time clock control register Operation mode control register LCD segment and I/O option register FSK decoder control register FSK decoder status register FSK packet data register LCD driver control register PFD control register PFD data register
General purpose RAM 00 01 02 03 04 05 06 07 08 09 0A 40~FF 40~FF 40~FF 40~FF 40~FF 40~FF 40~FF 40~FF 40~FF 40~FF 40~FF BANK0 RAM BANK1 RAM BANK2 RAM BANK3 RAM BANK4 RAM BANK5 RAM BANK6 RAM BANK7 RAM BANK8 RAM BANK9 RAM BANK10 RAM General purpose RAM space General purpose RAM space General purpose RAM space General purpose RAM space General purpose RAM space General purpose RAM space General purpose RAM space (HT95C300/30P only) General purpose RAM space (HT95C300/30P only) General purpose RAM space (HT95C300/30P only) General purpose RAM space (HT95C300/30P only) General purpose RAM space (HT95C300/30P only)
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BP Address Function LCD RAM display memory 1B 1B 1B 1B 40~57 40~6F 70~87 70~9F LCD RAM LCD RAM LCD RAM LCD RAM
HT95C200/20P/300/30P
Description
HT95C200/20P: LCD RAM mapping space for COM0~COM7 HT95C300/30P: LCD RAM mapping space for COM0~COM7 HT95C200/20P: LCD RAM mapping space for COM8~COM15 HT95C300/30P: LCD RAM mapping space for COM8~COM15
Indirect addressing register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] will access the memory pointed to by MP0 and MP1, respectively. Reading location [00H] or [02H] indirectly returns the result 00H, while writing it leads to no operation. MP0 is indirectly addressable in bank0, but MP1 is available for all banks by switch BP [04H]. If BP is unequal to 00H, the indirect addressing mode to read/write operation from 00H~3FH will return the result as same as the value of bank0. The memory pointer registers MP0 and MP1 are 8-bits registers, and the bank pointer register BP is 5-bits register. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can operate with immediate data. All data movement between two data memory locations must pass through the accumulator. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC)
* Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
The ALU not only saves the results of a data operation but also changes the status register. Status register - STATUS This status register contains the carry flag (C), auxiliary carry flag (AC), zero flag (Z), overflow flag (OV), power down flag (PD), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PD flags, bits in the status register can be altered by instructions, similar to the other registers. Data written into the status register will not change the TO or PD flag. Operations related to the status register may yield different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PD flag can be affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it.
Register
Label C
Bits 0
Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0
AC Z STATUS (0AH) OV PD TO 3/4
1 2 3 4 5 6, 7
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Interrupt The telephone controller provides an external interrupt, internal timer/event counter interrupt, a peripheral interrupt, an internal real time clock interrupt and internal dialer I/O interrupt. The Interrupt Control Registers 0 and Interrupt Control Register 1 both contains the interrupt control bits that set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by hardware clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0 (INTC1) may be set to allow interrupt nesting. If the stack is full, any other interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupt is triggered by a high to low transition of the INT/TMR1 pin and the interrupt request flag EIF will be set. When the external interrupt is enabled, the stack is not full and the external interrupt is active, a subRegister Label EMI EEI ET0I INTC0 (0BH) ET1I EIF T0F T1F 3/4 EPERI ERTCI EDRI INTC1 (1EH) 3/4 PERF RTCF DRF 3/4 Bits 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 R/W RW RW RW RW RW RW RW RO RW RW RW RO RW RW RW RO
HT95C200/20P/300/30P
routine call to location 04H will occur. The interrupt request flag EIF and EMI bits will be cleared to disable other interrupts. The Timer/Event Counter 0 interrupt is generated by a timeout overflow and the interrupt request flag T0F will be set. When the Timer/Event Counter 0 interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The interrupt request flag T0F and EMI bits will be cleared to disable further interrupts. The Timer/Event Counter 1 interrupt is generated by a timeout overflow and the interrupt request flag T1F will be set. When the Timer/Event Counter 1 interrupt is enabled, the stack is not full and the T1F bit is set, a subroutine call to location 0CH will occur. The interrupt request flag T1F and EMI bits will be cleared to disable further interrupts. The peripheral interrupt is activated when the burst-cycle is finished or the FSK decoder detect the ring signal or line reversal or FSK carrier signal or FSK packet data. When these interrupts occurred, the interrupt request flag PERF will be set. When the peripheral interrupt is enabled, the stack is not full and the PERF is set, a subroutine call to location 10H will occur. The interrupt request flag PERF and EMI bits will be cleared to disable other interrupts. The real time clock interrupt is generated by a 1Hz RTC generator. When the RTC time-out occurs, the interrupt request flag RTCF will be set. When the RTC interrupt is enabled, the stack is not full and the RTCF is set, a subroutine call to location 14H will occur. The interrupt request flag RTCF and EMI bits will be cleared to disable other interrupts.
Function Controls the master (global) interrupt (1=enabled; 0=disabled) Controls the external interrupt (1=enabled; 0=disabled) Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) Controls the Timer/Event Counter1 interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) Timer/Event Counter 0 request flag (1=active; 0=inactive) Timer/Event Counter1 request flag (1=active; 0=inactive) Unused bit, read as 0 Control the peripheral interrupt (1=enable; 0=disable) Control the real time clock interrupt (1=enable; 0=disable) Control the dialer I/O interrupt (1=enable; 0=disable) Unused bit, read as 0 Peripheral interrupt request flag (1=active; 0=inactive) Internal real time clock interrupt request flag (1=active; 0=inactive) Internal dialer I/O interrupt request flag (1=active: 0=inactive) Unused bit, read as 0
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The dialer I/O interrupt is triggered by any edge transition onto HKS pin or a falling edge transition onto HDI pin or a rising edge transition onto HFI pin, the interrupt request flag DRF will be set. When the dialer I/O interrupt is enabled, the stack is not full and the DRF is set, a subroutine call to location 18H will occur. The interrupt request flag DRF and EMI bits will be cleared to disable other interrupts. During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External interrupt Timer/Event Counter 0 interrupt Timer/Event Counter 1 interrupt Peripheral interrupt Real time clock interrupt Dialer I/O interrupt Priority of the interrupt EMI, EEI, ET0I, ET1I, EPERI, ERTCI and EDRI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (EIF, T0F, T1F, PERF, RTCF, DRF) are set by hardware or software, they will remain in the INTC0 or INTC1 registers until the interrupts are serviced or cleared by a software instruction. It is recommended that a program should not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator configuration There are two oscillator circuits in the controller, the external 32768Hz crystal oscillator and internal WDT OSC. Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
HT95C200/20P/300/30P
The 32768Hz crystal oscillator and frequency-up conversion circuit (32768Hz to 3.58MHz) are designed for dual system clock source. It is necessary for frequency conversion circuit to add external RC components to make up the low pass filter that stabilize the output frequency 3.58MHz (see the oscillator circuit). The WDT OSC is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the Idle mode (the system clock is stopped), the WDT OSC still works within a period of 78ms normally. When the WDT is disabled or the WDT source is not this RC oscillator, the WDT OSC will be disabled.
X1 X2 XC
15kW 3n 50n
System oscillator circuit Watchdog Timer - WDT The WDT clock source is implemented by a WDT OSC or external 32768Hz or an instruction clock (system clock divided by 4), determined by the mask option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. If the device operates in a noisy environment, using the on-chip WDT OSC or 32768Hz crystal oscillator is strongly recommended. When the WDT clock source is selected, it will be first divided by 512 (9-stage) to get the nominal time-out period. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 can give different time-out periods. The WDT OSC period is 78ms. This time-out period may vary with temperature, VDD and process variations. The WDT OSC always works for any operation mode.
32768H z W DT OSC S y s te m C lo c k /4 M ask O p tio n S e le c t W D T P r e s c a le r 9 - b it C o u n te r 7 - b it C o u n te r
W S0~W S2
8 -to -1 M U X W D T T im e - o u t
Watchdog Timer
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Register Label Bits R/W
HT95C200/20P/300/30P
Function
WDTS (09H)
WS0 WS1 WS2
0 1 2
RW
Watchdog Timer division ratio selection bits Bit 2, 1, 0=000, Division ratio=1:1 Bit 2, 1, 0=001, Division ratio=1:2 Bit 2, 1, 0=010, Division ratio=1:4 Bit 2, 1, 0=011, Division ratio=1:8 Bit 2, 1, 0=100, Division ratio=1:16 Bit 2, 1, 0=101, Division ratio=1:32 Bit 2, 1, 0=110, Division ratio=1:64 Bit 2, 1, 0=111, Division ratio=1:128 Unused bit. These bits are read/write-able.
3/4
7~3
RW
If the instruction clock is selected as the WDT clock source, the WDT operates in the same manner except in the Sleep mode or Idle mode. In these two modes, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic. If the WDT clock source is the 32768Hz, the WDT also operates in the same manner except in the Idle mode. When in the Idle mode, the 32768Hz stops, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic. The high nibble and bit3 of the WDTS are reserved for user defined flags, which can be used to indicate some specified status. The WDT time-out under Normal mode or Green mode will initialize chip reset and set the status bit TO. But in the Sleep mode or Idle mode, the time-out will initialize a warm reset and only the program counter and stack pointer are reset to 0. To clear the WDT contents (including the WDT prescaler), three methods are Register Label 3/4 UPEN MODE (26H) Bits 4~0 5 R/W RO RW
adopted; external reset (a low level to RES pin), software instruction and a HALT instruction. The software instruction include CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the mask option WDT instr. If the CLR WDT is selected (i.e. One clear instruction), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. Two clear instructions), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Controller operation mode Holteks telephone controllers support two system clock and four operation modes. The system clock could be 32768Hz or 3.58MHz and operation mode could be Normal, Green, Sleep or Idle mode. These are all selected by the software. The following conditions will force the operation mode to change to Green mode: Function
Unused bit, read as 0 1: Enable frequency up conversion function to generate 3.58MHz 0: Disable frequency up conversion function to generate 3.58MHz 1: Disable 32768Hz oscillator while the HALT instruction is executed (Idle mode) 0: Enable 32768Hz oscillator while the HALT instruction is executed (Sleep mode) 1: Select 3.58MHz as CPU system clock 0: Select 32768Hz as CPU system clock
MODE0
6
RW
MODE1
7
RW
Operation mode description HALT Instruction Not execute Not execute Be executed Be executed MODE1 1 0 0 0 MODE0 X X 0 1 UPEN 1 0 0 0 Operation Mode Normal Green Sleep Idle 32768Hz ON ON ON OFF 3.58MHz ON OFF OFF OFF System Clock 3.58MHz 32768Hz HALT HALT
Note: X means dont care
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* Any reset condition from any operation mode * Any interrupt from Sleep mode or Idle mode * Port A wake-up from Sleep mode or Idle mode
HT95C200/20P/300/30P
How to change the Operation Mode
* Normal mode to Green mode:
Clear MODE1 to 0, then operation mode is changed to Green mode but the UPEN status is not changed. However, UPEN can be cleared by software.
* Normal mode or Green mode to Sleep mode:
Once a Sleep mode or Idle mode wake-up event occurs, it will take SST delay time (1024 system clock period) to resume to Green mode. In other words, a dummy period is inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the Sleep mode or Idle mode. The Sleep mode or Idle mode is initialized by the HALT instruction and results in the following.
* The system clock will be turned off. * The WDT function will be disabled if the WDT clock
Step 1: Clear MODE0 to 0 Step 2: Execute HALT instruction After Step 2, operation mode is changed to Sleep mode, the UPEN and MODE1 are cleared to 0 by hardware.
* Normal mode or Green mode to Idle mode:
Step 1: Set MODE0 to 1 Step 2: Execute HALT instruction After Step 2, operation mode is changed to Idle mode, the UPEN and MODE1 are cleared to 0 by hardware.
* Green mode to Normal mode:
source is the instruction clock.
* The WDT function will be disabled if the WDT clock
source is the 32768Hz in Idle mode.
* The WDT will still function if the WDT clock source is
the WDT OSC.
* If the WDT function is still enabled, the WDT counter
Step 1: Set UPEN to 1 Step 2: Software delay 20ms at least Step 3: Set MODE1 to 1 After Step 3, operation mode is changed to Normal mode.
* Sleep mode or Idle mode to Green mode:
and WDT prescaler will be cleared and recounted again. * The contents of the on chip RAM and registers remain unchanged.
* All the I/O ports maintain their original status. * The flag PD is set and the flag TO is cleared by hard-
Method 1: Any reset condition occurred Method 2: Any interrupt is active Method 3: Port A wake-up Note The Timer0, Timer1, RTC and dialer I/O interrupt function will not work at the Idle mode because the 32768Hz crystal is stopped.
ware. Reset There are three ways in which a reset can occur.
* Power on reset. * A low pulse onto RES pin. * WDT time-out.
The reset conditions include power on reset, external reset, WDT time-out reset. By examining the processor status flag, PD and TO, the program can distinguish between different reset conditions. Refer to the Reset function for detailed description. The port A wake-up and interrupt can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by mask option. Awakening from Port A stimulus, the program will resume execution of the next instruction. Any valid interrupts from Sleep mode or Idle mode may cause two sequences. One is if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. The other is if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. It is necessary to mention that if an interrupt request flag is set to 1 before entering the Sleep mode or Idle mode, the wake-up function of the related interrupt will be disabled.
After these reset conditions, the Program Counter and Stack Pointer will be cleared to 0. To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system is reset or awakes from the Sleep or Idle operation mode.
V
DD
100kW RES 0 .1 m .
Reset circuit
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By examining the processor status flags PD and TO, the software program can distinguish between the different chip resets. TO 0 u 0 1 1 PD 0 u 1 u 1 Reset Condition Power on reset External reset during Normal mode or Green mode External reset during Sleep mode or Idle mode WDT time-out during Normal mode or Green mode WDT time-out during Sleep mode or Idle mode
HT95C200/20P/300/30P
The functional units chip reset status are shown below: Program Counter Interrupt Prescaler 000H Disabled Cleared Cleared After a master reset, WDT begins counting. (If WDT function is enabled by mask option)
WDT
Timer/Event Counter 0/1 Off Input/output Port Stack Pointer Input mode Points to the top of the stack
Note: u means unchanged
HALT W DT E x te rn a l RES SST 1 0 - b it R ip p le C o u n te r S y s te m R eset W D T T im e - o u t
W a rm R eset
VDD RES tS
ST
C o ld R e s e t
S S T T im e - o u t C h ip R eset
SYSC LK
Reset timing chart
Reset configuration When the reset conditions occurred, some registers may be changed or unchanged. Reset Conditions Register IAR0 MP0 IAR1 MP1 BP ACC PCL TBLP TBLH WDTS STATUS INTC0 TMR0H TMR0L TMR0C TMR1H TMR1L Addr. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H Power On xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ---0 0000 xxxx xxxx 0000H xxxx xxxx xxxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx xxxx xxxx RES Pin uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---0 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu uuuu uuuu RES Pin (Sleep/Idle) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---0 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu uuuu uuuu WDT uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---0 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --1u uuuu -000 0000 uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu uuuu uuuu WDT (Sleep/Idle) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu
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Reset Conditions Register TMR1C PA PAC PB PBC DialerIO PD PDC PE PEC INTC1 DTMFC DTMFD LINE RTCC MODE LCDIO FSKC FSKS FSKD LCDC PFDC PFDD Addr. 11H 12H 13H 14H 15H 16H 18H 19H 1AH 1BH 1EH 20H 21H 22H 24H 26H 28H 29H 2AH 2BH 2DH 2EH 2FH Power On 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 111x xxxx 1111 1111 1111 1111 ---- 1111 ---- 1111 -000 -000 -0-0 1001 0000 0000 0--- ---0-0- ---000- ---000- -----11 11-1 -x0- 1100 0000 0000 0000 -000 0000 ---0000 0000 x RES Pin 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 111x xxxx 1111 1111 1111 1111 ---- 1111 ---- 1111 -000 -000 -0-0 1001 0000 0000 u--- ---u-u- ---00u- ---uuu- -----11 11-1 -x0- 1100 0000 0000 uuuu -uuu 0000 ---0000 0000 u RES Pin (Sleep/Idle) 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 111x xxxx 1111 1111 1111 1111 ---- 1111 ---- 1111 -000 -000 -0-0 1001 0000 0000 u--- ---u-u- ---000- ---uuu- -----11 11-1 -x0- 1100 0000 0000 uuuu -uuu 0000 ---0000 0000 u
HT95C200/20P/300/30P
WDT 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 111x xxxx 1111 1111 1111 1111 ---- 1111 ---- 1111 -000 -000 -0-0 1001 0000 0000 u--- ---u-u- ---00u- ---uuu- -----11 11-1 -x0- 1100 0000 0000 uuuu -uuu 0000 ---0000 0000 u
WDT (Sleep/Idle) uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu -uuu -uuu -u-u uuuu uuuu uuuu u--- ---u-u- ---000- ---uuu- -----uu uu-u -xu- uuuu uuuu uuuu uuuu -uuu uuuu ---uuuu uuuu u
RAM (Data & LCD) Note:
u means unchanged x means unknown - means unused
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Timer/Event Counter Two timer/event counters (TMR0, TMR1) are implemented in the telephone controller series. The Timer/Event Counter 0 and Timer/Event Counter 1 contain 16-bits programmable count-up counter and the clock may come from an external source or internal source. For TMR0 internal source is instruction clock (system clock/4). For TMR1 internal source is 32768Hz. Using the 32768Hz clock or instruction clock, there is only one reference time-base. The external clock input allows the user to count external events, measure time intervals or pulse width, or generate an accurate time base. There are 3 registers related to Timer/Event Counter 0; TMR0H, TMR0L, TMR0C. Writing TMR0L only writes the data into a low byte buffer, but writing TMR0H simultaneously writes the data along with the contents of the low byte buffer into the Timer/Event Counter 0 preload register (16-bit). The Timer/Event Counter 0 preload register is changed by writing TMR0H operations. WritT im e r 0 : In s tr u c tio n c lo c k ( s y s te m T im e r 1 : 3 2 7 6 8 H z IN T /T M R 1 TM R0 TM 1 TM 0 TE c lo c k /4 )
HT95C200/20P/300/30P
ing TMR0L will keep the Timer/Event Counter 0 preload register unchanged. Reading TMR0H latches the TMR0L into the low byte buffer to avoid a false timing problem. Reading TMR0L returns the contents of the low byte buffer. In other words, the low byte of the Timer/Event Counter 0 can not be read directly. It must read the TMR0H first to make the low byte contents of Timer/Event Counter 0 be latched into the buffer. There are 3 registers related to the Timer/Event Counter 1; TMR1H, TMR1L, TMR1C. The Timer/Event Counter 1 operates in the same manner as the Timer/Event Counter 0. The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options. The Timer/Event Counter 1 has the same options as the Timer/Event Counter 0 and is defined by TMR1C. The timer/event counter control registers define the operating mode, counting enable or disable and active edge.
D a ta B u s T im e r /E v e n t C o u n te r 0 /1 P r e lo a d R e g is te r R e lo a d
TM 1 TM 0 TON
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
T im e r /e v e n t C o u n te r 0 /1
O v e r flo w to In te rru p t
Low
B y te B u ffe r
Timer/Event Counter 0/1 Register Label 3/4 Bits 0~2 R/W RO Unused bit, read as 0 To define the TMR0/TMR1 active edge of timer For event count or Timer mode (0=active on low to high; 1=active on high to low) For pulse width measurement mode (0=measures low pulse width; 1=measures high pulse width) To enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 To define the operating mode Bit 7, 6=01, Event count mode (external clock) Bit 7, 6=10, Timer mode Bit 7, 6=11, Pulse width measurement mode Bit 7, 6=00, Unused Function Timer/Event Counter 0 higher-order byte register Timer/Event Counter 0 lower-order byte register Timer/Event Counter 1 higher-order byte register Timer/Event Counter 1 lower-order byte register Function
TE TMR0C (0EH) TON TMR1C (11H) 3/4 TM0 TM1
3
RW
4 5
RW RO
6 7
RW
Register TMR0H (0CH) TMR0L (0DH) TMR1H (0FH) TMR1L (10H)
Bits 0~7 0~7 0~7 0~7
R/W RW RW RW RW
Rev. 0.10
19
October 1, 2002
Preliminary
The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR0 or INT/TMR1) pin. The timer mode functions as a normal timer with the clock source coming from instruction clock (TMR0) or 32768Hz (TMR1). The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0 or INT/TMR1). The counting is based on the 32768Hz clock for TMR1 or instruction clock for TMR0. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. If an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the corresponding interrupt request flag (T0F/T1F) at the same time. In pulse width measurement mode with the TON and TE bits equal to 1, once the TMR0/TMR1 pin has received a transient from low to high (or high to low; if the TE bit is 0) it will start counting until the TMR0/TMR1 pin returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only 1 cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and continue to measure the width and issues the interrupt request just like the other two modes. To enable the counting operation, the timer on bit (TON) should be set to 1. In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in the other two modes the TON can only be reset by instruction. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service. In the case of timer/event counter off condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter is reserved only in the timer/event counter preload register. The timer/event counter will go on operating until an overflow occurs. Input/output ports There are 28 bidirectional input/output lines in the telephone controller, labeled as PA, PB, PD and PE. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 18H or 1AH). Rev. 0.10 20
HT95C200/20P/300/30P
For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PDC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input can be reconfigured dynamically under software control. To make one I/O line to function as an input line, the corresponding latch of the control register must be written with a 1. The pull-high resistance shows itself automatically if the pull-high option is selected. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 18H or 1AH) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. They are selected by mask option per bit. There is a pull-high option available for all I/O lines. Once the pull-high option of an I/O line is selected, the I/O lines have pull-high resistor. Otherwise, the pull-high resistor is absent. It should be noted that a non-pull-high I/O line operating in input mode may cause a floating state. I/O port pull-high, wake-up function are selected by mask option I/O Port Input Output Pull-high Resistor Selected per bit Selected per bit HT95C300/30P: Selected per nibble HT95C200/20P: Selected per byte Selected per nibble Wake-up Function Selected per bit X
PA PB
CMOS CMOS
PD
CMOS
X
PE
CMOS
X
Note: X: unavailable F o r t h e H T 9 5 C 3 0 0 / 3 0 P, t h e P D 0 ~P D 7 a n d SEG36~SEG43 share the same pads. The PE0~PE3 and SEG44~SEG47 share the same pads. They can be selected per nibble by software option at any time.
October 1, 2002
Preliminary
Register Label 3/4 SPE0 LCDIO (28H) Bits 0~4 5 R/W RO RW Unused bit, read as 0
HT95C200/20P/300/30P
Function
For HT95C300/30P only 0: SEG44~SEG47 pins are LCD segment output 1: SEG44~SEG47 pins are PE0~PE3 pins For HT95C300/30P only 0: SEG36~SEG39 pins are LCD segment output 1: SEG36~SEG39 pins are PD0~PD3 pins For HT95C300/30P only 0: SEG40~SEG43 pins are LCD segment output 1: SEG40~SEG43 pins are PD4~PD7 pins For HT95C300/30P 0: COM0~COM7 are LCD common output 1: COM0~COM7 are unused pin For HT95C200/20P 0: COM0~COM7 are LCD common output 1: COM0~COM7 are PD0~PD7 pins terrupt occurs, its interrupt flag (RDETF, CDETF, FSKF) will be set to 1 by hardware even if the interrupt is disabled. These interrupts will cause a peripheral interrupt if the peripheral interrupt is enabled.When the peripheral interrupt occurs, the interrupt request flag PERF will be set and a subroutine call to location 10H will occur. Returning from the interrupt subroutine, the interrupt flag RDETF, CDETF or FSKF will not be cleared by hardware, the user should clear it by software. If interrupt flag RDETF is not cleared, next ring detect interrupt will be inhibited, other interrupt flags CDETF, FSKF have the same behavior. The power down mode (F_PWDN=1) will terminate all the FSK decoder function, however, the registers FSKC, FSKS and FSKD are accessible at this power down mode. Function FSK decoder power down 1: FSK decoder is at power down mode 0: FSK decoder is at operation mode Unused bit, read as 0 FSK packet data interrupt mask 1: Disable FSK packet data interrupt 0: Enable FSK packet data interrupt Ring or line reversal detect interrupt mask 1: Disable ring or line reversal detect interrupt 0: Enable ring or line reversal detect interrupt Carrier detect interrupt mask 1: Disable carrier detect interrupt 0: Enable carrier detect interrupt Select FSK packet data source 1: FSK packet data source is DOUTC 0: FSK packet data source is DOUT Unused bit, read as 0
SPD0
6
RW
SPD1
7
RW
LCDC (2DH)
VBIAS
1
RW
F o r t h e H T9 5 C 2 0 0 / 2 0 P, t h e P D 0~ P D 7 a n d COM0~COM7 share the same pads. They can only be selected per byte by software option at any time. When the PD0~PD7 or the PE0~PE3 are not selected, the I/O port control register (19H), PEC (1BH) could be read/write-able and be used as a general user RAM, but this function is not available for register PD (18H) and PE (1AH). FSK decoder The FSK decoder supports three interrupt sources to the peripheral interrupt vector. There are ring detect or line reversal detect, FSK carrier detect and FSK packet data. Write 0 to the control flag, RMSK, CMSK and FMSK will enable these interrupt. When any of these inRegister Label F_PWDN 3/4 FMSK Bits 0 1 2 R/W RW RO RW
FSKC (29H)
RMSK
3
RW
CMSK
4
RW
FSKSEL 3/4
5 6, 7
RW RO
Rev. 0.10
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October 1, 2002
Preliminary
Register Label Bits R/W
HT95C200/20P/300/30P
Function
RDETF
0
RW
Ring or line reversal detect interrupt flag 1: Ring or line reversal detected 0: No ring or line reversal detected This flag is set by hardware and cleared by software. FSK carrier detect interrupt flag 1: An FSK carrier signal is detected 0: No valid FSK carrier signal is detected This flag is set by hardware and cleared by software. This flag presents the FSK decoder output when the decoder is at operation mode. This data stream includes the alternate 1 and 0 pattern, the marking and the data. This flag present the FSK decoder output like as the DOUT flag but does not include the alternate 1 and 0 pattern. Unused bit, read as 0 FSK packet data interrupt flag 1: FSK packet data is ready 0: FSK packet data is not ready This flag is set by hardware and cleared by software. This flag presents the ring coming signal. Refer to the following figure. Unused bit, read as 0 FSK packet data register
CDETF
1
RW
FSKS (2AH)
DOUT
2
RO
DOUTC 3/4 FSKF
3 4
RO RO
5
RW
RINGF 3/4 FSKD (2BH) 3/4
6 7 7~0
RO RO RO
Ring or Line reversal detect When no signal is present on the telephone line, RDETI will be at GND and RTIME is pulled to VDD by R1. If a line reversal occurs, the RDETI pin will become high. This causes RTIME and internal signal R_DET to be pulled low. The C1 and R1 ensure that the R_DET signal is low during such a time, so that processor can detect it. When a ring occurs on the line, internal signal R_DET is permanently low, indicating the envelope of the ring. If the frequency of the ring must be measured, C1 may be removed, RTIME and R_DET inverter follow RDETI. The flag RDETF will go high when the R_DET signal falling edge is detected. This may cause a peripheral interrupt if RMSK is 0 and the peripheral interrupt is enabled (EPERI=1).
FSK data output The FSK decoder will decode the FSK signal on the TIP and RING line and produce two kinds of data formats, the serial data and the 8-bit packet data. It also provides the FSK carrier detection signal. To enable the FSK decoder, the F_PWDN should be written as 0. Once the FSK carrier signal is detected, the flag CDETF will be set to 1. This may cause a peripheral interrupt if CMSK is 0 and the peripheral interrupt is enabled. The serial FSK data is present in two formats: RAW data and COOK data, and could be monitored by the flag DOUT, DOUTC, respectively. The flag DOUT presents the output of the decoder when the decoder is at operation mode. This data stream includes the alternate 1 and 0 pattern, the marking and the data.
R IN G .
T IP R IN G
R_DET
L in e P r o te c tio n N e tw o rk
RDETI
C1
R T IM E
R1
V
DD
Rev. 0.10
22
October 1, 2002
Preliminary
2S R in g S ig n a l RDET. ._PW D N 0 .5 S 0 1 0 1 0 1 ... 1 1 1 1 1 ...
HT95C200/20P/300/30P
0 .5 S
.SK DATA
C le a r e d b y S o ftw a r e tS
UPD
S o ftw a re C o n tro l
CLO CK DOUT DOUTC
3 .5 8 M H z Raw DATA C ooked D A TA * 5 5 ...... S y n c S ig n a l 8 - b it P a c k e te d . S K D A T A M a r k S ig n a l D A T A S ig n a l
. S K D a ta
Note: *: If the flag FSKSEL=1, the sync signal data will not be packeted.
The flag DOUTC presents the output of the decoder when the decoder is at operation mode. This data stream is like the DOUT flag but does not include the alternate 1 and 0 pattern. If the FSK data is not detected, the DOUT and DOUTC are held high. Beside the serial data, the decoder also provides FSK packet data. When decoder receives an FSK signal, it will packet 10 bits data to 8 bits data, the first and 10th bits will be discarded. When the 8-bit packet data is valid, it will be stored in the FSK data register FSKD, the FSK packet data interrupt flag FSKF will be set to 1. This may cause a peripheral interrupt if FMSK is 0 and the peripheral interrupt is enabled. The FSK packet source could be DOUT or DOUTC, selected by FSKSEL. Note that the start bit of the 10 packet bit should be 0, so the MARK signal (one of the FSK data signals) will not be packeted. To detect the carrier signal or decode the serial data or packet 10-bit data to 8-bit data, the operation mode of the controller must be selected in Normal mode (processor running with 3.58MHz). When the operation mode is Green or Sleep, FSK decoder will decode the wrong signal. However, when the operation mode is Green or Sleep mode and the FSK decoder is at power down mode (F_PWDN=1), the ring and line reversal detect is still functional.
DTMF generator The DTMF (Dual Tone Multiple-Frequency) signal generator is implemented in the telephone controller. It can generate 16 dual tones and 8 single tones from the DTMF pin. This generators also support power down, tone on/off, burst mode function. The DTMF generator clock source is 3.58MHz, before using this function, the system operation mode must be at Normal mode. The generator supports one interrupt source to the peripheral interrupt vector, namely DTMF burst-cycle interrupt. Write 0 to the control flag, BMSK will enable this interrupt. When the DTMF generator finishes 1 burst-cycle, the interrupt flag BURSTF will be set to 1 by hardware even if the interrupt is disabled. This interrupt will cause a peripheral interrupt if the peripheral interrupt is enabled. When the peripheral interrupt occurs, the interrupt request flag PERF will be set and a subroutine call to location 10H will occur. Return from the interrupt subroutine, the interrupt flag BURSTF will not be cleared by hardware, the user could clear it by software if necessary. If this flag is not cleared, next burst interrupt will occur. The power down mode (D_PWDN=1) will terminate all the DTMF generator function, however, the registers DTMFC and DTMFD are accessible at this power down mode.
Rev. 0.10
23
October 1, 2002
Preliminary
Register Label D_PWDN 3/4 TONE Bits 0 1 2 R/W RW RO RW
HT95C200/20P/300/30P
Function
DTMF generator power down 1: DTMF generator is at power down mode. 0: DTMF generator is at operation mode. Unused bit, read as 0 Tone output enable 1: DTMF signal output is enabled. 0: DTMF signal output is disabled. Burst-cycle interrupt mask 1: No interrupt will occur when 1 burst-cycle is finished. 0: An interrupt will occur when 1 burst-cycle is finished. This flag is functional only at Burst-mode. Burst-mode bit 1: Enable Burst-mode. 0: Disable Burst-mode. Unused bit, read as 0 Burst-cycle interrupt flag 1: One burst-cycle is finished. 0: No burst-cycle is finished. This flag is set by hardware and cleared by software. This flag is functional only at Burst-mode. Unused bit, read as 0 To set high group frequency To set low group frequency
BMSK DTMFC (20H) BURST 3/4
3
RW
4 5
RW RO
BURSTF
6
RW
3/4 DTMFD (21H) TC4~TC1 TR4~TR1
7 3~0 7~4
RO RW RW
The DTMF pin output is controlled by the combination of the D_PWDN, TONE, TR~TC value. Control Register Bits D_PWDN 1 0 0 0 TONE x 0 1 1 TR4~TR1/TC4~TC1 x x 0 Any valid value DTMF Pin Output Status 0 1/2 VDD 1/2 VDD 16 dual tones or 8 signal tones, bias with 1/2 VDD
* How to start the Burst-Mode

The DTMF generator supports two output modes, namely Tone-Mode and Burst-Mode. Tone-Mode: (D_PWDN=0, TONE=1 and BURST=0).
* The duration of Tone-Mode output should be handled
At Tone-Mode, set BURST flag to 1. If D_PWDN flag=0 & TONE flag=0, set BURST flag=1, then set TONE flag=1. If D_PWDN flag=1, set BURST flag & TONE flag=1, then clear D_PWDN flag=0.
by the software.
* DTMFD register value could be changed as desired,
the DTMF pin will output the new dual-tone simultaneously.
* BMSK and BURSTF flags are not necessary. * Any time set BURST flag to 1, the DTMF output mode
* The burst-cycle processing:
will be changed to Burst-Mode, and Burst-Cycle is starting. Burst-Mode: (D_PWDN=0, TONE=1 and BURST=1).
* The timing of Burst-Mode output is controlled by hard-
ware.
Step 1: DTMF pin automatically generates DTMF tone (determined by the TC~TR register value) for 82.5ms. Step 2: DTMF pin automatically generates 1/2 VDD for 85.5ms. Step 3: After the 85.5ms timeout, the TC~TR value is cleared to 0 by hardware. Step 4: One burst-cycle is finished. The DTMF burst-cycle interrupt is generated. Step 5: Jump to Step 1 for the next burst-cycle.
Rev. 0.10
24
October 1, 2002
Preliminary
Precaution must be taken during Burst-mode operation:
* DTMF pin will output 1/2 VDD during next burst-cycle
HT95C200/20P/300/30P
* When the burst-cycle starts, if the user changes the
if the user does not initialize the TC~TR value again.
* When the burst-cycles starts, if the user clears the
BURST flag to 0 before Step 2 is finished, Step 3 and Step 4 will be executed and after step 4 is executed, DTMF output mode will be changed to Tone-Mode. * When the burst-cycle starts, if the user clears the BURST flag to 0 after Step 3 is executed, then Step 4 and Step 5 will be executed. After next Step 4 is executed, DTMF output mode will be changed to Tone-Mode. * When the burst-cycles starts, if the user clears the TONE flag to 0, DTMF output will be changed to 1/2 VDD.
TC~TR value at Step1, DTMF pin output will also be changed (determined by the new TR~TC value). The DTMF output duration of burst-cycle is constantly 82.5ms. * When the burst-cycle starts, if the user changes the TC~TR value at Step2, DTMF pin still outputs 1/2 VDD. The DTMF output duration of burst-cycle is constantly 85.5ms.
* If the next burst-cycle is executed continuously, Step
4 and Step 5 occur simultaneously.
D_PD W N=1
D_PD W N=0 and BURST=0
1 /2 V D D TO NE=0
TO NE=1
TO NE=0
TO NE=1
TO NE=1
TO NE=0
A ll th e tim in g o f th e T O N E = 1 a n d T O N E = 0 a r e d e te r m in e d b y s o ftw a r e
DTMF Tone_mode
D_PD W N=1 D_PD W N=0 BURST=1 8 2 .5 m s 8 5 .5 m s 8 2 .5 m s 8 5 .5 m s 8 2 .5 m s 8 5 .5 m s
1 /2 V D D
S te p 1 In itia l N e w T C -T R
S te p 2 T im in g S te p 3
S te p 1
S te p 2 S te p 3
S te p 1
S te p 2
TO NE=1
TO NE=0
TO NE=1 In itia l N e w T C - T R T im in g
D T M . O n e B u r s t_ C y c le . in is h e d In te r r u p t
S te p 4
S te p 4
DTMF Burst_mode Tone frequency Output Frequency (Hz) Specified 697 770 852 941 1209 1336 1477 Actual 699 766 847 948 1215 1332 1472 % Error +0.29% -0.52% -0.59% +0.74% +0.50% -0.30% -0.34%
% Error does not contain the crystal frequency shift Rev. 0.10 25 October 1, 2002
Preliminary
DTMF frequency selection table: register DTMFD[21H] Low Group TR4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 TR3 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 TR2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 TR1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 TC4 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 High Group TC3 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 TC2 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
HT95C200/20P/300/30P
DTMF Output TC1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 Low 697 697 697 697 770 770 770 770 852 852 852 852 941 941 941 941 High 1209 1336 1477 1633 1209 1336 1477 1633 1209 1336 1477 1633 1209 1336 1477 1633
DTMF Code 1 2 3 A 4 5 6 B 7 8 9 C * 0 # D
Single tone for testing only 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 697 770 852 941 1209 1336 1477 1633
Writing other values to TR4~TR1, TC4~TC1 may generate an unpredictable tone.
Rev. 0.10
26
October 1, 2002
Preliminary
Dialer I/O function
HT95C200/20P/300/30P
A special dialer I/O circuit is built into the telephone controller for dialing application. These specially designed I/O cells allows the controller to work under a low voltage condition that usually happens when the subscribers loop is long. Dialer I/O pin function: Name XMUTE I/O NMOS Output Description XMUTE pin output is controlled by software. This is an NMOS open drain structure pulled to VSS during dialing signal transmission. Otherwise, it is an open circuit. XMUTE is used to mute the speech circuit when transmitting the dialer signal. DNPO pin is an NMOS output, usually by means of software to make/break the line. This pin is only controlled by software. This pin is controlled by the HKS, HFI and HDI pins. When PO pin is high, the telephone line is make. When PO pin is low, the telephone line is break. This pin controls the PO pin directly. This pin is used to monitor the status of the hook-switch and its combination with HFI/HDI can control the PO pin output to make or break the line. A rising edge to HKS pin will cause the dialer I/O to be on-hook status and generate an interrupt, its vector is 18H. A falling edge to HKS pin will cause the dialer I/O to be off-hook status and clear HFO and HDO flags to 0. This falling edge will also generate an interrupt, its vector is 18H. This pin is controlled directly by HDI, HKS and HFI pin. When HDO pin is high, the hold-line function is enabled and PO outputs a high signal to make the line. A low pulse to HDI pin (hold-line function request) will clear HFO to 0 and toggle HDO and generates an interrupt, its vector is 18H. This pin controls the HFO and HDO pins directly. This pin is functional only when the line is made, that is, off-hook or hand-free (PO output high signal). This pin is controlled directly by HFI, HDI and HKS pins. When HFO pin is high, the hand-free function is enabled and PO outputs a high signal to make the line. A high pulse to HFI pin (hand-free function request) will clear HDO to 0 and toggle HFO and generates an interrupt, its vector is 18H. This pin controls the PO, HFO and HDO pins directly.
DNPO
NMOS Output
PO
CMOS Output
HKS
Schmitt Trigger Input
HDO
CMOS Output
HDI
Schmitt Trigger Input
HFO
CMOS Output
HFI
Schmitt Trigger Input
The following are the recommended circuit for HFI and HDI pins.
V
DD
10kW H . I P in 0 .1 m . In te r n a l P u ll- lo w 200kW 10kW 0 .1 m . H D I P in
V
DD
In te r n a l P u ll- h ig h 2 0 0 k W
Rev. 0.10
27
October 1, 2002
Preliminary
Phone controller also supports the dialer I/O flag to monitor the dialer status. Register Label HFI HFO HDI HDO HKS SPO SDNPO XMUTE Bits 0 1 2 3 4 5 6 7 R/W RO RO RO RO RO RW RW RW 1: The HFI pin level is 1. 0: The HFI pin level is 0. 1: The HFO pin level is 1. 0: The HFO pin level is 0. 1: The HDI pin level is 1. 0: The HDI pin level is 0. 1: The HDO pin level is 1. 0: The HDO pin level is 0. 1: The HKS pin level is 1. 0: The HKS pin level is 0.
HT95C200/20P/300/30P
Function
DIALERIO (16H)
1: The PO pin is controlled by the combination of the HKS, HFI and HDI pin. 0: The PO pin level is set to 0 by software. 1: The DNPO pin level is set to floating by software. 0: The DNPO pin level is set to 0 by software. 1: The XMUTE pin is set to floating by software. 0: The XMUTE pin is set to 0 by software.
The SPO flag is special designed to control the PO. When the flag SPO is set to 1, the PO pin is controlled by the combination of the HKS pin, HFI pin and HDI pin. The PO pin will always be 0 if the flag SPO=0. The relation between the Dialer I/O function (SPO=1) Dialer Function On-hook On-hook & Hand-free On-hook & Hold-line Off-hook Off-hook & Hand-free Off-hook & Hold-line Dialer I/O Pin (Flag) Status HKS 1 1 1 0 0 0 HFO 0 1 0 0 1 0 HDO 0 0 1 0 0 1 PO 0 1 1 1 1 1 DNPO floating floating floating floating floating floating Result Telephone Line break make make make make make
The following describes the dialer I/O function status machine figure: Off-hook: A falling edge to HKS pin
HDI O n -h o o k H.I O ff-h o o k H a n d -fre e H.I HDI HDI O ff-h o o k H o ld - lin e O n -h o o k O n -h o o k H.I O ff-h o o k O ff-h o o k O n -h o o k H o ld - lin e HDI H.I HDI O ff-h o o k O n -h o o k O ff-h o o k O n -h o o k H a n d -fre e
On-hook: A rising edge to HKS pin HFI: A high pulse to HFI pin (Hand-free request is generated.) HDI: A low pulse to HDI pin (Hold-line request is generated.)
Rev. 0.10
28
October 1, 2002
Preliminary
Line control function Register LINE (22H) Label 3/4 LINEC Bits 6~0 7 R/W RO RW Unused bit, read as 0 1: Enable the line control function 0: Disable the line control function
HT95C200/20P/300/30P
Function
The line control function is enabled by the flag LINEC Conditions LINEC 1 1 1 Operation Mode Normal or Green mode Sleep mode Idle mode Source to Enable Line Control Function RTC time out interrupt Port A wake-up RTC time out interrupt Port A wake-up
When the line control source is activated, the PO pin will be set to high signal. Clearing LINEC to 0 will terminate the line control function and drive PO pin outputs low signal.
RTC In te rru p t
P o r t A W a k e - u p fu n c tio n L IN E C
L in e C o n tr o l C ir c u it
PO
=1
E n a b le /D is a b le
RTC function Register Label 3/4 RTCC (24H) RTCEN RTCTO Bits 6, 4~0 5 7 R/W RO RW RW Unused bit, read as 0 1: Enable RTC function 0: Disable RTC function 1: RTC time-out occurs 0: RTC time-out not occurs Function
The real time clock (RTC) is used to supply a regular internal interrupt. Its time-out period is 1000ms. If the RTC time-out occurs, the interrupt request flag RTCF and the RTCTO flag will be set to 1. The interrupt vector for the RTC is 14H. When the interrupt subroutine is serviced, the interrupt request flag (RTCF) will be cleared to 0, but the flag RTCTO remain in its original value. If the RTCTO flag is not cleared, next RTC time-out interrupt will occur. Low battery detection The phone controller provides a circuit that detects the LBIN pin voltage level. To enable this detection function, the LBEN should be written as 1. Once this function is enabled, the detection circuit needs 50ms to be stable. After that, the user could read the result from LBFG. The low battery detect function will consume power. For power saving, write 0 to LBEN if the low battery detection function is unnecessary.
V R
1
DET
1 .1 5 V R e fe r e n c e V o lta g e
LB.G
2
R
L B IN LBEN
The battery low threshold is determined by external R1 and R2 resistors. 1.15= VDET R2 1.15 (R1+ R2) (R) VDET= R1+ R2 R2 1.15 (R1+ R2) (R) R1=1.087R2 R2
If we want to detect VDET=2.4V then 2.4V=
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Preliminary
LCD driver The LCD driver can directly drive an LCD panel with 1/8 duty and 1/4 bias or with 1/16 duty and 1/5 bias, this function is selected by the flag VBIAS. The frame of this LCD driver may select a 64Hz or 128Hz by flag FRAME. LCD driver uses the voltage of the VLCD pin as the power source. To adjust the view angle, the programmer can select the real LCD power by the flags VCON0 and VCON1. The flag LCDON is used to turn On/Off the LCD display. Note that the VLCD voltage must equal or be less than VDD and VDD2.
HT95C200/20P/300/30P
Segment/Common to I/O selection For the flexible purpose, some of the LCD COMMON and SEGMENT pins are shared with the input/output port. HT95C300/30P provides 12 pins to be selected to SEGMENT output pins or I/O pins. HT95C200/20P provides 8 pins to be selected for COMMON output pins or I/O pins. Both of the HT95C300/30P and HT95C200/20P provide the LCD COMMON output pins for 8 COMMON or 16 COMMON. The description of the relation between segment pins, common pins and I/O pins are shown on the next page. Function LCD frame selection 0: LCD frame is 64Hz 1: LCD frame is 128Hz LCD BIAS selection 0: select 1/16 duty and 1/5 bias, COM0~COM15 are available 1: select 1/8 duty and 1/4 bias, only COM8~COM15 are available When the 8 COM is selected HT95C300/30P: COM0~COM7 will be optioned to unused pins HT95C200/20P: COM0~COM7 are disabled, PD0~PD7 are available Low battery detection switch 0: disable the low battery detection 1: enable the low battery detection Unused bit, read as 0 Low battery detection flag 1: LBIN pin voltage is less than 1.25V 0: LBIN pin voltage is not less than 1.25V LCD contrast adjusting Bit6,5=00: LCD voltage supply is 0.66VLCD Bit6,5=10: LCD voltage supply is 0.82VLCD Bit6,5=01: LCD voltage supply is 0.93VLCD Bit6,5=11: LCD voltage supply is 1.00VLCD 1: Turn on the LCD display 0: Turn off the LCD display Unused bit, read as 0 For HT95C300/30P only 0: SEG44~SEG47 pins are LCD segment output 1: SEG44~SEG47 pins are PE0~PE3 pins For HT95C300/30P only 0: SEG36~SEG39 pins are LCD segment output 1: SEG36~SEG39 pins are PD0~PD3 pins For HT95C300/30P only 0: SEG40~SEG43 pins are LCD segment output 1: SEG40~SEG43 pins are PD4~PD7 pins
Register
Label FRAME
Bits 0
R/W RW
VBIAS
1
RW
LBEN LCDC (2DH) 3/4 LBFG
2 3 4
RW RO RO
VCON0 VCON1
5 6
RW
LCDON 3/4 SPE0 LCDIO (28H)
7 0~4 5
RW RO RW
SPD0
6
RW
SPD1
7
RW
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Preliminary
LCD display memory
HT95C200/20P/300/30P
The phone controller provides an area on embedded data memory for LCD display. The LCD display memory are located at bank 1BH and can be read and written to, only by indirect addressing mode using MP1. When data is written into the display data area it is automatically read by the LCD driver which then generates the corresponding LCD driving signals, to turn the display On or Off, a 1 or 0 is written to the corresponding bit of the display memory, respectively. All of the LCD display memories are with random values after the power on reset and unchanged after other reset conditions. COM7 to COM0 for HT95C200/20P Address 40H 41H 3/4 56H 57H Register Name SEG0 SEG1 3/4 SEG22 SEG23 Bit 7 COM7 COM7 COM7 COM7 COM7 Bit 6 COM6 COM6 COM6 COM6 COM6 Bit 5 COM5 COM5 COM5 COM5 COM5 Bit 4 COM4 COM4 COM4 COM4 COM4 Bit 3 COM3 COM3 COM3 COM3 COM3 Bit 2 COM2 COM2 COM2 COM2 COM2 Bit 1 COM1 COM1 COM1 COM1 COM1 Bit 0 COM0 COM0 COM0 COM0 COM0
COM15 to COM8 for HT95C200/20P Address 70H 71H 3/4 86H 87H Register Name SEG0 SEG1 3/4 SEG22 SEG23 Bit 7 COM15 COM15 COM15 COM15 COM15 Bit 6 COM14 COM14 COM14 COM14 COM14 Bit 5 COM13 COM13 COM13 COM13 COM13 Bit 4 COM12 COM12 COM12 COM12 COM12 Bit 3 COM11 COM11 COM11 COM11 COM11 Bit 2 COM10 COM10 COM10 COM10 COM10 Bit 1 COM9 COM9 COM9 COM9 COM9 Bit 0 COM8 COM8 COM8 COM8 COM8
Note: When VBIAS bit set to 1 for 8 COM operation (248), the LCD RAM only map to (70H~87H). COM7 to COM0 for HT95C300/30P Address 40H 41H 3/4 6EH 6FH Register Name SEG0 SEG1 3/4 SEG46 SEG47 Bit 7 COM7 COM7 COM7 COM7 COM7 Bit 6 COM6 COM6 COM6 COM6 COM6 Bit 5 COM5 COM5 COM5 COM5 COM5 Bit 4 COM4 COM4 COM4 COM4 COM4 Bit 3 COM3 COM3 COM3 COM3 COM3 Bit 2 COM2 COM2 COM2 COM2 COM2 Bit 1 COM1 COM1 COM1 COM1 COM1 Bit 0 COM0 COM0 COM0 COM0 COM0
COM15 to COM8 for HT95C300/30P Address 70H 71H 3/4 9EH 9FH Register Name SEG0 SEG1 3/4 SEG46 SEG47 Bit 7 COM15 COM15 COM15 COM15 COM15 Bit 6 COM14 COM14 COM14 COM14 COM14 Bit 5 COM13 COM13 COM13 COM13 COM13 Bit 4 COM12 COM12 COM12 COM12 COM12 Bit 3 COM11 COM11 COM11 COM11 COM11 Bit 2 COM10 COM10 COM10 COM10 COM10 Bit 1 COM9 COM9 COM9 COM9 COM9 Bit 0 COM8 COM8 COM8 COM8 COM8
Note: When VBIAS bit is set to 1 for 8 COM operation (488), the LCD RAM only map to (70H~9FH).
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PFD generator Register Label 3/4 PFDEN PFDC (2EH) Bits 3~0 4 R/W RO RW Unused bit, read as 0
HT95C200/20P/300/30P
Function
1: Enable PFD output 0: Disable PFD output, the MUSIC pin output low level. Bit6, 5=00: Prescaler output= PFD frequency source/1 Bit6, 5=01: Prescaler output= PFD frequency source/2 Bit6, 5=10: Prescaler output= PFD frequency source/4 Bit6, 5=11: Prescaler output= PFD frequency source/8 1: The PFD frequency source is 3.58MHz/4 0: The PFD frequency source is 32768Hz PFD data register
PRES0 PRES1
5 6
RW
FPFD PFDD (2FH) 3/4
7 7~0
RW RW
The PFD (programmable frequency divider) is implemented in the phone controller. It is composed of two portions: a prescaler and a general counter. The prescaler is controlled by the register bits, PRES0 and PRES1. The general counter is programmed by an 8-bit register PFDD. The source for this generator can be selected from 3.58MHz/4 or 32768Hz. To enable the PFD output, write 1 to the PFDEN bit. The PFDD is inhibited to write while the PFD is disabled. To modify the PFDD contents, the PFD must be enabled. When the generator is disabled, the PFDD is cleared by hardware.
P r e s c a le r O u tp u t M U S IC
32768H z 3 .5 8 M H z /4
P r e s c a le r
P.DD
P.D O u tp u t P.DEN
PR ES1,PR ES0
PFD output frequency=
Prescaler output , where N=the value of the PFDD 2 (N + 1)
Mask option table The following shows many kinds of mask options in the telephone controller. All these options should be defined in order to ensure proper system functions. Name Mask Option WDT source selection RC(R)Select the WDT OSC to be the WDT source. T1(R)Select the instruction clock to be the WDT source. 32kHz(R)Select the external 32768Hz to be the WDT source. Disable(R)Disable WDT function. This option defines how to clear the WDT by instruction. One clear instruction(R)The CLR WDT can clear the WDT. Two clear instructions(R)Only when both of the CLR WDT1 and CLR WDT2 have been executed, then WDT can be cleared. Port A wake-up selection. Define the activity of wake-up function. All port A have the capability to wake-up the chip from a HALT. This wake-up function is selected per bit. Pull-high option. This option determines whether the pull-high resistance is viable or not. Port A pull-high option is selected per bit. Port B pull-high option is selected per bit. Port D pull-high option is selected per nibble for HT95C300/30P. Port D pull-high option is selected per byte for HT95C200/20P. Port E pull-high option is selected per nibble.
WDT
WDTinstr
Wake-up PA
Pull-high Port A Pull-high Port B Pull-high Port D Pull-high Port E
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Preliminary
Application Circuits
22M W T ip O ff-h o o k A92 R in g 100kW 10m. 3 .3 k W A42 100kW 47kW H a n d fre e 0 .0 2 m . 10kW 270kW V 5 .1 V 0 .1 m . 100m. V
DD
HT95C200/20P/300/30P
100kW O n -h o o k 330kW 1N4148 2 .2 k W 1m. 1N4148 1N4148
1N4148
220kW 33kW
1 .5 k W
150kW
220kW
1m. B a tte ry 1 .5 3 = 4 .5 V
S peech N e tw o rk 100kW
DD
0 .1 m .
H.I I/O
PO
HDI
VDD
HKS
H.O
DTM . XM UTE M U S IC V
DD
0 .1 m .
0 .0 1 m . T ip
200kW
VLCD T IP RES
100kW 0 .1 m .
0 .2 m . 470kW
R in g 0 .2 m . 0 .0 1 m . 200kW 33kW
RDETI R IN G
V 270kW
H T 9 5 C 2 0 0 /2 0 P /3 0 0 /3 0 P
DD
V R T IM E 0 .2 m . L B IN
DD
MEMORY D IA L IN G
STORE HOLD
AM PM
ABR
MON
TUE
W ED
THR
.RI
SAT
SUN
COMMON
SEGMENT LCD Pannel I/O I/O X1 X2 XC 15kW 1 2 4 5 7 8 0 # * /T 9 6 3 K ey1 K ey2 K ey3 K ey4 K ey5 K ey6 K ey7 K ey8 K ey9 K ey10 K ey11 K ey12 32768H z 3n. 50n. VSS
K e y M a tr ix
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Preliminary
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Description
HT95C200/20P/300/30P
Instruction Cycle
Flag Affected
Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory
1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1)
Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt Description
HT95C200/20P/300/30P
Instruction Cycle Flag Affected
2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2
None None None None None None None None None None None None None
2(1) 2(1)
None None
1 1(1) 1(1) 1 1 1 1(1) 1 1
None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged.
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Preliminary
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O Add data memory and carry to the accumulator
HT95C200/20P/300/30P
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
C O
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
C O
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
C O
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
C O
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
C O
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AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 CALL addr Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 Logical AND accumulator with data memory
HT95C200/20P/300/30P
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
C 3/4
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
C 3/4
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
C 3/4
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr
Operation Affected flag(s)
TC2 3/4 CLR [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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CLR [m].i Description Operation Affected flag(s) TC2 3/4 CLR WDT Description Operation Affected flag(s) TC2 3/4 CLR WDT1 Description TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 Clear bit of data memory
HT95C200/20P/300/30P
The bit i of the specified data memory is cleared to 0. [m].i 0
C 3/4
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are cleared. WDT 00H PD and TO 0
C 3/4
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CLR WDT2 Description
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CPL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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Preliminary
CPLA [m] Description
HT95C200/20P/300/30P
Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TC2 3/4 DAA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TC2 3/4 DEC [m] Description Operation Affected flag(s) TC2 3/4 DECA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HALT Description Enter power down mode
HT95C200/20P/300/30P
This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0
Operation
Affected flag(s) TC2 3/4 INC [m] Description Operation Affected flag(s) TC2 3/4 INCA [m] Description Operation Affected flag(s) TC2 3/4 JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 NOP Description Operation Affected flag(s) TC2 3/4 OR A,[m] Description Operation Affected flag(s) TC2 3/4 OR A,x Description Operation Affected flag(s) TC2 3/4 ORM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 Move immediate data to the accumulator
HT95C200/20P/300/30P
The 8-bit data specified by the code is loaded into the accumulator. ACC x
C 3/4
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
C 3/4
No operation No operation is performed. Execution continues with the next instruction. PC PC+1
C 3/4
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
C 3/4
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
C 3/4
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
C 3/4
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RET Description Operation Affected flag(s) TC2 3/4 RET A,x Description Operation Affected flag(s) TC2 3/4 RETI Description Operation Affected flag(s) TC2 3/4 RL [m] Description Operation Affected flag(s) TC2 3/4 RLA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 Return from subroutine
HT95C200/20P/300/30P
The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
C 3/4
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
C 3/4
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1
C 3/4
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
C 3/4
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
C 3/4
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Preliminary
RLC [m] Description Operation Rotate data memory left through carry
HT95C200/20P/300/30P
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TC2 3/4 RLCA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TC2 3/4 RR [m] Description Operation Affected flag(s) TC2 3/4 RRA [m] Description Operation Affected flag(s) TC2 3/4 RRC [m] Description Operation TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TC2 3/4 Rev. 0.10 TC1 3/4 TO 3/4 PD 3/4 43 OV 3/4 Z 3/4 AC 3/4 C O October 1, 2002
Preliminary
RRCA [m] Description
HT95C200/20P/300/30P
Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TC2 3/4 SBC A,[m] Description Operation Affected flag(s) TC2 3/4 SBCM A,[m] Description Operation Affected flag(s) TC2 3/4 SDZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TC2 3/4 SDZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 0.10
44
October 1, 2002
Preliminary
SET [m] Description Operation Affected flag(s) TC2 3/4 SET [m]. i Description Operation Affected flag(s) TC2 3/4 SIZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
HT95C200/20P/300/30P
C 3/4
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
C 3/4
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TC2 3/4 SIZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TC2 3/4 SNZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 0.10
45
October 1, 2002
Preliminary
SUB A,[m] Description Operation Affected flag(s) TC2 3/4 SUBM A,[m] Description Operation Affected flag(s) TC2 3/4 SUB A,x Description Operation Affected flag(s) TC2 3/4 SWAP [m] Description Operation Affected flag(s) TC2 3/4 SWAPA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O Subtract data memory from the accumulator
HT95C200/20P/300/30P
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
C O
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
C O
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
C O
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
C 3/4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
C 3/4
Rev. 0.10
46
October 1, 2002
Preliminary
SZ [m] Description Skip if data memory is 0
HT95C200/20P/300/30P
If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TC2 3/4 TABRDC [m] Description Operation Affected flag(s) TC2 3/4 TABRDL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 0.10
47
October 1, 2002
Preliminary
XOR A,[m] Description Operation Affected flag(s) TC2 3/4 XORM A,[m] Description Operation Affected flag(s) TC2 3/4 XOR A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 Logical XOR accumulator with data memory
HT95C200/20P/300/30P
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
C 3/4
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
C 3/4
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
C 3/4
Rev. 0.10
48
October 1, 2002
Preliminary
Package Information
128-pin QFP (1420) outline dimensions
C D 102
HT95C200/20P/300/30P
H 65 G I
103
64
.
A B
E
128
39
K 1 38 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.80 13.90 24.80 19.90 3/4 3/4 2.50 3/4 3/4 0.65 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.50 0.20 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 0.95 0.20 7
Rev. 0.10
49
October 1, 2002
Preliminary
HT95C200/20P/300/30P
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 0.10
50
October 1, 2002

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